fn9008 rev 2.00 page 1 of 10 march 2004 fn9008 rev 2.00 march 2004 isl6118 dual power supply controller datasheet the isl6118 is a dual channel, fully independent overcurrent (oc) fault protection ic for the +2.5v to +5.5v environment. this device features internal current monitoring, accurate current limiting, integrated power switches and current limited delay to latch-of f for system protection. the isl6118 current sense and limiting circuitry sets the current limit to a nominal 0.6a, which is well suited for the 3.3v aux acpi application . the isl6118 is the ideal companion chip to the hip1 011d and hip1011e dual pci hot plug controllers. together these and the isl6118 fully control the four legacy pci vol tages (12v, +3.3v, +5v) and the 3.3v aux, respectively, for power control of two pci slots compliant to pci bus p ower management interface spec rev 1.1. designed to be co-located with the hip1011d on the motherboar d, the isl6118 pr ovides oc fault notification, accurate current l imiting and a consistent timed latch-off thus isolating and prot ecting the voltage bus in the presence of an oc event or shor t circuit during all pci bus power states as defined by the pci specification. the 12ms time to latch-off is independen t of the adjoining switchs electrical or thermal conditio n and the oc response time is inversely related to the oc magnitude. each isl6118 incorporates in a single 8-lead soic package two 80m ? n-channel mosfet power switches for power control. each switch is driven by a constant current source giving a cont rolled ramp up of the output voltage. this provides a soft s tart turn-on e liminating bus voltage drooping caused by inrush current while charging heavy load capacitances. independent enabling inputs and fault reporting outputs for each channel are compatible with 3v and 5v logic to allow external control and monitoring. the isl6118 undervoltage (uv) feature prevents turn-on of the outputs unless the correct enable state and vin > 2.5v are present. during initial turn-on the isl6118 prevents fault reporting by blank ing the fault signal. rising and falling outputs are current-limited voltage ramps so that both the inrush current and v oltage slew rate are limited, independent of load. this reduces supply droop due to surge and eliminates the need for external emi filters. during operation, once an oc condition is detected the appropriate output is current limited for 12ms to allow transient conditions to pass. if still in current limit after t he current limit period has elapsed, the output is latched off and the fault is reported by pulling the corresponding fault low. the fault signal is latched low until reset by the enable signal being de-asserted at which time the fault signal will clear. features ? 80m ? integrated power n-c hannel mosfet switches ? accurate current sensing and limiting ? 12ms fault delay to latch-off, no thermal dependency ? 2.5v to 5.5v operating range ? disabled output internally pulled low ? undervoltage lockout ? controlled turn-on ramp time ? channel independent fault output signals ? channel independent logic level enable high inputs (isl6118h) or enable low inputs (isl6118l) ? pb-free package options available ? tape & reel packing with - t part number suffix applications ? acpi 3.3v aux control ? electronic circuit limiting and breaker pinout isl6118 (soic) top view ordering information part # temp. range (c) pkg. pkg. dwg. # isl6118lib -40 to 85 8 ld soic m8.15 isl6118libza (note) -40 to 85 8 ld soic (pb-free) m8.15 ISL6118HIB -40 to 85 8 ld soic m8.15 ISL6118HIBza (note) -40 to 85 8 ld soic (pb-free) m8.15 isl6118eval1 isl6118 evaluation platform isl6ahpeval1 acpi (hip1011d and isl6118h) evaluation platform note: intersil pb-free products emp loy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-f ree soldering operations. intersil p b-free products are msl classif ied at pb-free peak reflow temperatures that meet or exceed the pb-fre e requirements of ipc/jedec j std-020b. gnd vin enable_1 enable_2 1 2 3 4 8 7 6 5 fault_1 out_1 out_2 fault_2 n o t r e co m m e n de d f o r n e w de s i g n s n o r e c o m m e nd e d r e p l ac e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t s c
isl6118 fn9008 rev 2.00 page 2 of 10 march 2004 simplified block diagram gnd vin en_1 en_2 fault_2 out_2 out_1 fault_1 q-pump current and temp. por channel 1 like channel 2 monitoring, gate and output control logic pin no. designator function description 1 gnd ic reference 2 vin chip bias, controlled supply input, undervoltage lock-out vin provides chip bias voltage. at vin < 2.5v chip functionalit y is disabled, fault_x latch is cleared and floating and out is held low. 3, 4 enable_1, 2/ enable_1, 2 channel enable/ enable not inputs enables/disables switch. 5, 8 f ault out_2, 1 channel 2, 1 overcurrent fault not indicator channel overcurrent fault-not indicator. fault floats and is di sabled until vin > 2.5v. this output is pulled low after the oc timeout period has expired an d stays latched until enable is deasserted. 6, 7 out_2, 1 channel 2,1 controlled supply output channel voltage output, connect to load to protect. upon an oc condition out is current limited to 0.6a. current limit response time is within 200s. t his output will remain in current limit for a determined time before being latched off.
isl6118 fn9008 rev 2.00 page 3 of 10 march 2004 absolute maximum ratings thermal information supply voltage (vin to gnd). . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0v en, fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd-0.3v to vin +0.3v output current . . . . . . . . . . . . . . . . . . . . . . . sh ort circuit protected esd rating human body model (per mil-std-883 method 3015.7) . . . . 3kv operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to 85c supply voltage range (typical). . . . . . . . . . . . . . . . . . 2.7v to 5.5v thermal resistance (typical, note 1) ? ja (c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ? ja is measured with the component mounted on a high effective the rmal conductivity test board in free air. see tech brief tb379 for details. 2. all voltages are relative to g nd, unless otherwise specified. electrical specifications supply voltages = 3.3v, t a = t j = -40 to 85c, unless otherwise specified parameter symbol test conditions min typ max units power switch isl6118 on resistance at 2.7v r ds(on)_27 vin = 2.7v, i out = 0.4a, t a = t j = 25c - 90 105 m ? t a = t j = 85c - 115 130 m ? isl6118 on resistance at 3.3v r ds(on)_33 vin = 3.3v, i out = 0.4a, t a = t j = 25c - 80 100 m ? t a = t j = 85c - 115 130 m ? isl6118 on resistance at 5.0v r ds(on)_50 vin = 5v, i out = 0.4a, t a = t j = 25c - 80 95 m ? t a = t j = 85c - 115 130 m ? disabled output voltage v out_dis vin = 5v, switch disabled, 50 ? a load - 300 450 mv out rising rate t_vout_rt r l = 10 ??? c l = 0.1 ? f, 10%-90% - 8 - v/ms slow v out turn-off rate t_svout_offt r l = 10 ??? c l = 0.1 ? f, 90%-10% - 8 - v/ms fast v out turn-off rate t_fvout_offt r l = 1 ??? c l = 0.1 ? f, 90%-10% - 4 - v/ ? s current control current limit, vin = 3.3v - 5v ilim v out = 0.8v 0.45 0.6 0.75 a oc regulation settling time tsett ilim r l = 3 ??? c l = 0.1 ? f to within 10% of cr - 2 - ms severe oc regulation settling time tsett ilim_sev r l < 1 ??? c l = 0.1 ? f to within 10% of cr - 100 - ? s overcurrent latch-off time t oc_loff isl6118x, t j = 25c - 12 - ms i/o parameters fault output voltage v fault fault output current = 10ma - - 0.4 v enable high threshold ven_vih vin = 5.5v 2.0 - - v enable low threshold at 2.7v ven_vil vin = 2.7v - - 0.6 v enable low threshold at 5.5v ven_vil vin = 5.5v - - 0.8 v enable input current ien_i enable = 0v to 5v, vin = 5v, t j > 25c -0.5 0 0.5 ? a bias parameters enabled vin current i vdd switches closed, output = open, t j > 0c - 120 200 ? a disabled vin current i vdd switches open, output = open - 1 5 ? a undervoltage lockout threshold v uvlh vin rising, switch enabled 1.7 2.25 2.5 v uv hysteresis uv hys 50 100 - mv over temperature disable temp_dis - 150 - c
isl6118 fn9008 rev 2.00 page 4 of 10 march 2004 introduction the isl6118 is a fully independent dual channel overcurrent (oc) fault protection ic for th e +2.5v to +5.5v environment. each isl6118 incorporates in a single 8-lead soic package two 80mw n-channel mosfet power s witches for power control. see figure 2 for integrated fet on resist ance curves. independent enabling inputs and fault reporting outputs compatible with 3v and 5v logic allow for external control and monitoring. this device features internal current monitoring, accurate current limiting, integr ated power switches and curren t limited timed delay to latch-o ff for system protection. key feature description and operation uv lockout the isl6118 undervoltage (uvlo) lockout prevents functionality of the device unl ess the correct enable state and vin > 2.5v are present. soft start a constant 500na current source ramps up the switchs gate causing a voltage follower effect on the output voltage. this provides a soft start turn-on and eliminates bus voltage drooping caused by inrush current charging heavy load capacitances. rising and falling outputs are current limited voltage ramps so that both the inrush current and voltage slew rate are limited, independent of load. this reduces supply droop due to surge and also elim inates the need for external emi filters necessary on other i c products. see figure 3 for soft start waveforms. fault blanking on start-up during initial turn-on the isl6118 prevents nuisance faults fro m being reported to the system controller by blanking the fault signal for 12ms. this blanking eliminates the need for external rc filters necessary for other vendors products. current regulation the isl6118 has integrated current sensing on the power mosfets that allows for rapid control of oc events. once an oc condition is detected the i sl6118 goes into its current regulation (cr) control mode. the isl6118 cr level is set to a nominal 0.6a and is regulated to within 25% over full temperature, bias voltage range and oc magnitude. the speed of this control is proport ional to the level of oc. thus a hard oc is more quickly contro lled than a marginal condition. see figures 4 through 7 for cu rrent regulation performance curves and waveforms. latch-off time delay the primary function of any oc p rotection device is to quickly isolate the voltage bus from a faulty load. unlike other manufacturers ic products that sense the ic thermal condition to isolate a faulty load, the isl6118 uses an internal 12ms timer that starts upon oc detec tion. once an oc condition is detected, the appropri ate output is curren t limited for 12ms to allow transient conditions to pa ss before latch-off. the time t o latch-off is independent of the devices thermal or adjacent switchs electrical condition. see figur e 10 for waveforms illustrating independent latch-off. if, after the isl6118 has latched off, and the fault has assert ed and the enable is not deasserted but the oc condition still exists, the isl6118 (unlike other ic devices) does not send to the controller a continuous str ing of fault pulses. the isl6118 s single fault signal is sent at the time of latch off. slow and fast shutdown the isl6118 has two shutdo wn modes. when disabled with a load current less than the curre nt regulation (cr) level the isl6118 shuts down in a cont rolled manner using a 500na constant current source controlled ramp. when disabled during cr or if the timer has expired t he isl6118 quickly pulls down the output thereb y quickly removing the faulted load from the voltage bus. see figures 8 and 9 for illustrative waveforms of each shutdown mode. over temperature shutdown although the isl6118 has a thermal shutdown feature, because of the 12ms timed shutdown this will only be invoked in extremely high ambient temperatures. active output pulldown another unique isl6118 feature is the active pull down on the outputs to 300mv above gnd when the device is disabled. figure 1 illustrates the is l6118 operational waveforms, showing the relationships bet ween the various i/o signals during typical and faulted cond itions. it also graphically highlights many of the terms and modes of operation referred to in this data sheet. using the isl6118eval1 platform general and biasing information the isl6118eval1 platform, fi gure 14, allows evaluation of the isl6118 dual power supply control ic and comparison against a suitably sized pptc component. the evaluation platform is bia sed and monitored through numerous test points (tp#). see table 1 for test point assignments and descriptions. table 1. isl6118eval1 t est point assignments tp # description tp1 eval board and ic gnd tp2 eval board +3.3v bias tp3 enable switch 1 tp4 enable switch 2 tp5 switch 2 fault tp6 switch out 2 tp7 switch out 1 tp8 switch 1 fault tp9 ic vin pin tp10 pptc load side tp11 invoke overcurrent
isl6118 fn9008 rev 2.00 page 5 of 10 march 2004 typical performance curves figure 1. operational waveforms figure 2. switch on resistance at 0.4a figure 3. v out soft start vs c l and prop delay, r l = 8 ? figure 4. current regulation vs v out (vin = 3.3v) figure 5. current regulation vs v out (vin = 5v) i out 12ms current regulation period reset by current regulation settling time (1.4ms) enable 0.6a current limit overcurrent v out off on enable fault latch-off set -40-30-20-10 0 102030405060708090 temperature (c) 40 50 60 70 80 90 100 110 120 100 vin = 3.3v vin = 5v vin = 2.7v switch on resistance (m ? ) time (400s/div) v out voltage (0.5v/div) t pd c l = 100f c l = 10f 560s v out enable c l = 0.1f 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0 v out (v) 3.1 i out (ma) 500 550 600 650 700 85c 25c -40c 1.3 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v out (v) 4.8 500 550 600 650 700 85c -40c 25c i out (ma)
isl6118 fn9008 rev 2.00 page 6 of 10 march 2004 figure 6. oc to cr settling time waveforms figure 7. cr settling t ime vs fault current figure 8. slow turn-off vs c l, r l = 8 ? figure 9. fast turn-off vs c load figure 10. switch fault independence typical performance curves (continued) time (200s/div) output current (1a/div) nominal current 0.4a current regulated level 0.6a 1 23456789101112 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 fault current (a) 0 time to current regulation (ms) v out voltage (0.5v/div) time (400s/div.) c l = 10f c l = 100f v out c l = 0.1f enable v out voltage (0.5v/div) time (400s/div) c l = 10f c l = 100f v out c l = 0.1f voltage (0.5v/div) time (4ms/div) vin isl6118 out 1 isl6118 out 2
isl6118 fn9008 rev 2.00 page 7 of 10 march 2004 using the isl6118eval1 platform upon proper bias the pptc, f1, has a nominal 400ma load current passing through it which is the hold current rating for that particular device. removal of the pptc is necessary to isolate the isl6118 as the pptc load current is common to the isl6118eval1 bias connections. by enabling either or both of the isl6118h switches by signaling tp3 and/or tp4 high (> 2.4v) these switches are also loaded with a nominal 400ma current. provided test points enable t he evaluation of voltage loss across the pptc (tp9 - tp10) and likewise across the isl6118 enabled switches (tp9 - tp6 and tp7). expect to see 100% - 300% greater voltage l oss across the pptc than the isl6118 (see figure 11 for isl6118 vs pptc voltage loss comparison). an overcurrent (oc) condition can be invoked on both the isl6118 and the pptc by drivi ng tp11 to +6v, causing sw1 to close and a nominal 0.94m a load is imposed. this represents a current overload to the isl6118 and is thus quickly current regulated to the 600ma limit. if the oc duratio n extends beyond the nominal 1 2ms of the internal isl6118 timer then the outpu t is latched off and the fault output is asserted by being pulled low turning on the appropriate fault led. (please note: the labelin g for the fault-1 and fault-2 is reversed.) the ev al board is designed to only invoke a oc condition on channel 2 (tp4) so that a channel to channel isolation evaluation in the pres ence of a oc condition can be evaluated. the primary func tion of any oc protection device is to quickly isolate the voltage bus from a f aulty load. unlike the pptc and other vendor available ic product s, the isl6118 internal timer that starts upon oc detection pr ovides consistent protection that is independent of temperat ure. figures 11 through 13 illustrate the comparative efficiency and effectiveness of the isl6118 vs the pptc in protectin g and isolating a faulty load capable from drooping the sy stem bus in that system. figure 11. isl6118 vs pptc into 8.2 ? load figure 12. isl6118 vs pptc into 3.5 ?? load figure 13. isl6118 vs pptc with extended 3.5 ? load typical performance curves (continued) voltage (0.5v/div) v vin 3.32v isl6118 v out 3.29v (0.075 ? ) 0.4a hold current pptc 2.93v (1.1 ? ) gnd voltage (0.5v/di v) time (4ms/div) vin isl6118 cr 12ms period 0.4a hold current pptc out isl6118 out voltage (0.5v/div) time (4s/div) isl6118 out 0.4a hold current pptc out vin 2.3v at 10s 1.5v at 30s
isl6118 fn9008 rev 2.00 page 8 of 10 march 2004 figure 14. isl6118eval1 schematic and photograph 1 2 3 4 8 7 6 5 en2 fault_out2 vin out1 out2 en1 isl6118 (vin) isl6118eval1 fault_out1 c1 c2 c4 r1 r3 r5 d1 d2 d3 d5 r6 r7 r8 r10 f1 sw1 tp2 c3 r2 r4 d4 r9 tp3 tp4 tp9 tp10 tp6 tp7 table 2. isl6118eval1 board component listing component designator component function component description dut1 isl6118 intersil, ISL6118HIB 3.3v aux hot plug controller r1 - r3 410ma nominal load resistors yageo, 8 ??? 5%, 2w, 8w-2-nd r4 - r5 970ma current over load resistors yageo, 6 ??? 5%, 2w, 6w-2-nd r6 - r10 led current limiting resistor 470 ? , 0805 c1 decoupling capacitor 0.1 ? f, 0805 c2 - c4 load capacitor 100 ? f, 16v electrolytic, radial lead d1 - d5 indicating leds 0805, smd leds red f1 pptc (polymer positive temperat ure coefficient) raychem, poly switch, rxe040 or equivalent sw1(q1) current over load invoking switch access tp11 fairchild, itf86110dk8t, 7.5a, 30v, 0.025 ? , dual n-channel, logic level power mosfet
isl6118 fn9008 rev 2.00 page 9 of 10 march 2004 implementing autoreset on the isl6118h hot swap controllers abstract in applications where the cost, complexity or requirement for a system controller is avoided a nd an autonomous power control function is desired, a device t hat can monitor and protect against excessive cu rrent failures is needed. this shows how to implement such an autonom ous controller using the ISL6118HIB. this application works only with the h version of these devices. the h version refers to the enable function being asserted up on a high input. introduction the isl6118, isl6119 and isl 6121 are all 2.5v to 5v power supply controllers, each having a different level of current regulation (cr). the isl6118 and isl6119 have 2 independent controllers with cr levels of 0.6a and 1.0a respectively whereas the isl6121 is a single supply controller with a 2a cr level. each of these devices features integrated power switch(es) for power control. e ach switch is driven by a constant current sour ce giving a controlled ramp up of the output voltage. this provides a s oft start turn-on eliminating bus voltage drooping caused by in-rush current while charging heavy load capacitances. the independent enabling inputs and fault reporting outputs for each channel are available and necessary for the autonomous autoreset application. the undervoltage (uv) feature pre vents turn-on of the outputs unless the enable pin and vin are >2.5v. during initial turn- on the isl6118 prevents fault re porting by blanking the fault signal. rising and falling output s are current-limited voltage ramps so that both the inrush current and voltage slew rate are limited, independent of load. thi s reduces supply droop due to surge and eliminates the need fo r external emi filters. during operation, once an oc condition is detected the appropriate output is current lim ited to the appropriat e level for 10ms to allow transient conditions to pass. if still in current limit a fter the current limit period has elapsed, the output is la tched off and the fault is repor ted by pulling the corresponding fault low. the fault signal is latched low un til reset by the enable signal being de-asserted a t which time the fault signal will clear. it is this described sequence of events that allows for the autoreset function to be implem ented in a cost efficient manner requiring the addition of only an rc network per channel to the typical application. figure 15 illustrates the rc network needed with suggested component values and the configur ation of the relevant pins for each autoreset channel. description of operation initially as voltage is applied to vin, the pull up resistor (r pu) provides for pull up to vin on bo th the enable pin asserting th e output once vin > 2.5v and on the fltn pin. once turned on and an overcurrent (oc) condition occurs the ic provides cr protection for 10ms and then the fltn pin pulls low through rpu and also pulling the enable low thus resetting the device fault condition. at this time the rpu charges the cap and the voltage on the enable/fltn node rises un til the enable > 2.0 and the output is asserted on once again. this automatic reset cycle wi ll continue until the oc f ault no longer exist s on the output. aft er several seconds in this mode of operation the ic thermal protection invokes adjusting the timing o f the on-off cycle to prevent excessive thermal di ssipation in the power switch protecting itself and surrounding circuitry. see figure 16 for operation waveform. . applications ?usb ? 2.5v to 5v up to 10w power port protection figure 15. vin enable fltn gnd isl6118h rpu = 2k c = 0.1f figure 16. auto reset operation iout 1a/div vout 2v/div vin/fltn 5v/div 0a 0v 4ms/div
fn9008 rev 2.00 page 10 of 10 march 2004 isl6118 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2001-2004. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m ? notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gat e burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm ( 0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions . inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greate r above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millime ter. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 ? 0 8 0 8 - rev. 0 12/93
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